• Fast Read Access Times – Flash: 70 ns and 90 ns – SRAM: 70 ns and 90 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Word-Program Time: 14 祍 (typical) – Chip Rewrite Time: SST32HF802: 8 seconds (typical) SST32HF162/164: 15 seconds (typical)
• Flash Automatic Erase and Program Timing – Internal VPP Generation
• Flash End-of-Write Detection – Toggle Bit – Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available – 48-lead TSOP (12mm x 20mm) – 48-ball TBGA (10mm x 12mm)
Product Description The SST32HF802/162/164 ComboMemory devices integrate a 512K x16 or 1M x16 CMOS flash memory bank with a 128K x16 or 256K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high performance SuperFlash technology.
Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 14 祍ec. The entire flash memory bank can be erased and programmed word-by-word in typically 8 seconds for the SST32HF802 and 15 seconds for the SST32HF162/164, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST32HF802/ 162/164 devices contain on-chip hardware and software data protection schemes.The SST32HF802/162/164 devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years.
The SST32HF802/162/164 devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration.
The SST32HF802/162/164 provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs Sector-Erase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled erase or program cycle in the flash bank has commenced, the SRAM bank can be accessed for read or write.
The SST32HF802/162/164 devices are suited for applications that use both flash memory and SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF802/162/164 devices significantly improve performance and reliability, while lowering power consumption, when compared with multiple chip solutions. The SST32HF802/162/164 inherently use less energy during erase and program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles.
特种存储器: FLASH+SRAM
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